Synopsys ASIC Digital Design, Engineer

Job Overview

Synopsys is seeking an ASIC Digital Design Engineer in Hyderabad for verification of high-speed interconnect IP such as PCIe, UCIe and DDR. The role involves UVM testbenches, SystemVerilog assertions, test planning, functional coverage, regression debugging and readiness for silicon delivery.

Eligibility

B.Tech or M.Tech in Electronics, VLSI, Electrical Engineering or related discipline; 2+ years in hands-on ASIC/SoC verification, with familiarity with UVM, SystemVerilog and at least one high-speed protocol.

Skills Mentioned

Key Responsibilities

• 1Plan and execute ASIC/SoC verification for PCIe, UCIe and DDR IP.
• 2Build reusable UVM agents, sequencers, scoreboards and coverage models.
• 3Write SystemVerilog constrained-random tests and assertions.
• 4Debug simulations and regressions using VCS, Verdi and coverage tools.
• 5Analyze protocol compliance issues, coverage gaps and root causes.
• 6Document verification results and collaborate with design and validation engineers.

Who Should Apply?

Applicants who meet the employer's stated eligibility and role-specific requirements; read the official job posting before applying.

Quick eligibility check

Eligibility at a Glance

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Role breakdown

What This Role Involves

The official listing is for ASIC Digital Design, Engineer at Synopsys in Hyderabad, Telangana, India. Based on the published information, the main areas to review include SystemVerilog, UVM, PCIe, UCIe.

• Plan and execute ASIC/SoC verification for PCIe, UCIe and DDR IP.
• Build reusable UVM agents, sequencers, scoreboards and coverage models.
• Write SystemVerilog constrained-random tests and assertions.

Employer information

About Synopsys on This Listing

Synopsys is the employer named on the official source used for this job. HD Careers verified this listing against careers.synopsys.com. This section only shows facts available from the verified job record.

Resume & interview focus

Skills to Demonstrate

Use these as evidence prompts, not as keywords to add without real experience.

• SystemVerilog

  This skill is mentioned for the role. If you include it on your resume, connect it to a real work, internship or project example you can explain.

• UVM

  This skill is mentioned for the role. If you include it on your resume, connect it to a real work, internship or project example you can explain.

• PCIe

  This skill is mentioned for the role. If you include it on your resume, connect it to a real work, internship or project example you can explain.

• UCIe

  This skill is mentioned for the role. If you include it on your resume, connect it to a real work, internship or project example you can explain.

• DDR

  This skill is mentioned for the role. If you include it on your resume, connect it to a real work, internship or project example you can explain.

• VCS

  This skill is mentioned for the role. If you include it on your resume, connect it to a real work, internship or project example you can explain.

Preparation

Before You Apply

• 1Review your hands-on examples for SystemVerilog, UVM, PCIe.
• 2Prepare one clear example related to this responsibility: Plan and execute ASIC/SoC verification for PCIe, UCIe and DDR IP..
• 3Keep your employment dates, degree details and contact information consistent across your resume and the employer application form.
• 4Use the official employer page as the final source if any requirement, deadline or application step changes.

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Source & Verification

Source: Synopsys Careers

Last checked by HD Careers: 12 Oct 2026

Job information can change after publication. The employer's official page is the final source for eligibility, deadlines and application availability.

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